At the SPIE Advanced Lithography conference in San Jose, CA, imec and its partners will present a patterning solution for a 42nm-pitch M1 layer and a 32nm-pitch M2 layer in logic design compatible with the foundry N5 requirements.   The approach includes two scenarios for EUVL insertion that, when combined with an array of scaling boosters, serve as a basis of the industry requirements for power, performance, area and cost. Including proposals for design rules, masks, photoresists, etching and...